Solar cells are devices that convert light energy into electrical energy, based on a characteristic of a semiconductor.
The solar cells have a PN junction structure where a positive (P)-type semiconductor and a negative (N)-type semiconductor are joined to each other. When sunlight is incident on a solar cell having the PN junction structure, a hole and an electron are generated in the semiconductors by energy of the incident sunlight. At this time, due to an electric field which is generated in a PN junction, the hole (+) moves to the P-type semiconductor, and the electron (−) moves to the N-type semiconductor, thereby generating an electric potential to produce power.
The solar cells may be categorized into wafer type solar cells and thin film type solar cells.
The wafer type solar cells are solar cells which are manufactured by using a semiconductor material itself, such as a silicon wafer, as a substrate. The thin film type solar cells are solar cells which are manufactured by forming a semiconductor on a substrate such as glass in a thin film type.
The wafer type solar cells are better in efficiency than the thin film type solar cells, and the thin film type solar cells have an advantage where the manufacturing cost is reduced in comparison with the wafer type solar cells.
Therefore, solar cells based on a combination of the wafer type solar cell and the thin film type solar cell have been proposed. Hereinafter, a related art solar cell will be described with reference to the drawings.
FIGS. 1A to 1E are schematic process cross-sectional views illustrating a process of manufacturing a solar cell according to an embodiment of the related art.
First, as seen in FIG. 1A, a semiconductor wafer 10 is prepared.
Subsequently, as seen in FIG. 1B, a first semiconductor layer 20 is formed on an upper surface of the semiconductor wafer 10, and a second semiconductor layer 30 is formed on a lower surface of the semiconductor wafer 10. In this case, due to a process characteristic, the first semiconductor layer 20 is formed up to a side surface of the semiconductor wafer 10 as well as the upper surface of the semiconductor wafer 30, and the second semiconductor layer 30 is formed up to the side surface of the semiconductor wafer 10 as well as the lower surface of the semiconductor wafer 10. Therefore, as illustrated, the first semiconductor layer 20 and the second semiconductor layer 30 may be connected to each other at the side surface of the semiconductor wafer 10.
Subsequently, as seen in FIG. 1C, a first transparent conductive layer 40 is formed on an upper surface of the first semiconductor layer 20, and a second transparent conductive layer 50 is formed on a lower surface of the second semiconductor layer 30. In this case, due to the process characteristic, the first transparent conductive layer 40 is formed up to a side surface of the first semiconductor layer 20 as well as the upper surface of the first semiconductor layer 20, and the second transparent conductive layer 50 is formed up to a side surface of the second semiconductor layer 30 as well as the lower surface of the second semiconductor layer 30. Therefore, as illustrated, the first transparent conductive layer 40 and the second transparent conductive layer 50 may be connected to each other at the side surface of the semiconductor wafer 10.
Subsequently, as seen in FIG. 1D, a first electrode 60 is formed on an upper surface of the first transparent conductive layer 40, and a second electrode 70 is formed on a lower surface of the second transparent conductive layer 50.
Subsequently, as seen in FIG. 1E, a separation part 80 is formed by removing an edge area of each of the first transparent conductive layer 40, the first semiconductor layer 20, and the semiconductor wafer 10.
An electrical connection between the first transparent conductive layer 40 and the second transparent conductive layer 50 which is made at the side surface of the semiconductor wafer 10 is cut off by the separation part 80, and an electrical connection between the first semiconductor layer 20 and the second semiconductor layer 30 which is made at the side surface of the semiconductor wafer 10 is cut off by the separation part 80, thereby preventing occurrence of short circuit therebetween.
However, the method of the related art has the following drawbacks.
First, in the related art, the separation part 80 is formed for preventing short circuit in the above-described process of FIG. 1E, and in this case, a carrier such as a hole or an electron is trapped in the separation part 80 area, causing a problem where an efficiency of the solar cell is reduced.
Moreover, referring to an enlarged view referred to by an arrow of FIG. 1E, particles 90 which are pollutant components can be located on the upper surface of the first transparent conductive layer 40 and the lower surface of the second transparent conductive layer 50. The particles 90 can occur in a process of forming the first transparent conductive layer 40 and the second transparent conductive layer 50 and can also occur in a process of forming the separation part 80. As described above, if the particles 90 are located on the upper surface of the first transparent conductive layer 40 and the lower surface of the second transparent conductive layer 50, a transmittance of sunlight is reduced by the particles 90, and moreover, a flow of a current is hindered by the particles 90, causing a problem where an efficiency of the solar cell is reduced.